In the semiconductor manufacturing industry, front-end silicon wafer fabrication operations produce a number of integrated circuit dies, such as memory devices. Back-end operations separate, package, and test individual dies. At wafer sort and after packaging of a memory device, back-end testing of the memory device determines whether any memory cells in the memory device are defective. In a multi-plane flash memory, the memory cells in each plane are tested for operability and any defective memory cells in a particular plane are identified. Fuses are used to map defective memory cells to redundant memory cells. What is needed is a technique for improving programming time of fuse links in a multi-plane Flash memory that are used to provide redundant columns or sectors that are identified during back-end testing.